1. Technical Field
The present invention is related to a flash memory device, and more particularly, to a flash memory device capable of reducing noise in common source line, a program verify method thereof, and a memory system including the same.
2. Discussion of Related Art
The semiconductor memory device may be generally divided into a volatile memory device, for example, DRAM and SRAM, and a non-volatile memory device, for example, EEPROM, FRAM, PRAM, MRAM and flash memory. A volatile memory device loses stored data when power supply is cut off, but a nonvolatile memory device retains stored data even when power supply is cut off. A flash memory has characteristics such as high programming speed, low consumption of power, and large capacity data storage. Flash memory is therefore used widely as a storage means in computer system and the like.
A flash memory includes a memory cell array that stores data. A memory cell array includes a plurality of memory blocks. The memory blocks each include a plurality of pages. The pages each include a plurality of memory cells. The memory cells may each be either an on-cell or an off-cell according to a threshold voltage distribution of the cell. An on-cell may be considered an erased cell, and an off-cell may be considered a programmed cell. A flash memory performs an erase operation in units of a memory block. This means that in order to erase a memory cell, an entire memory block of memory cells must be erased. A flash memory performs a write or read operation in units of a page. This means that in order to write or read a memory cell, an entire page of memory cells must be written or read.
A flash memory has a cell string structure. A cell string includes a string selection transistor connected to a string selection line SSL, a memory cell connected to a plurality of word lines WL0-WL31, and a ground selection transistor connected to a ground selection line GSL. The string selection transistor is connected to a bit line BL and the ground selection transistor is connected to a common source line CSL.
A flash memory may be able to store either a single bit of data in each memory cell or multiple bits of data may be stored in each memory cell, depending on the type of memory cells used. In general, a memory cell that stores single bit data is called a Single Level Cell (SLC), and a memory cell that stores multiple bits data is called a Multi Level Cell (MLC). The Single Level Cell has an erase state based on threshold voltage and one program state. The Multi Level Cell has an erase state based on threshold voltage and a plurality of program states.
In a flash memory having a Multi Level Cell, margins between each of the states are provided by narrowing the width of the threshold voltage distribution of each state. Noise generated in the common source line CSL may cause the threshold voltage distribution width of each state to be widened and this may reduce or eliminate the margins between each of the states and may therefore reduce reliability. Noise occurs when voltage drops due to resistance in the common source line CSL.
The common source line CSL is generally connected to a ground terminal via a metal line. A voltage drop occurs when current flows through the common source line CSL due to resistance on the metal line. The voltage drop in the common source line CSL is proportionate to the current that flows through the common source line CSL. Accordingly, the voltage drop increases when the current flow increases, and the voltage drop decreases when the current flow decreases. When a common source line voltage is generated due to voltage drop in the common source line CSL, the threshold voltage distribution of the memory cell may be widened.